The present invention is directed toward the field of integrated circuit (IC) barrier structures and methods, and more particularly toward multi-layer TiW structures for preventing undesired diffusion of conductor materials within the IC structures.
Barrier layers are employed in conventional integrated circuits adjacent to composite or layered metal lines including conductor materials used for interconnecting devices within integrated circuits fabricated on silicon chips. The metal lines are fabricated from electrical conductor material, such as AlCu or AlSiCu for example, sandwiched between straddling "barrier layers" of refractory metal or metallic alloy material, for example TiW, an alloy of 10-30 atomic % Ti in W.
These barrier layers are conventionally provided for many reasons including the effective prevention of the interaction of the conductor materials such as aluminum for example with adjacent structures and materials for example adjacent silicon structures, according to a phenomenon called "spiking." The phenomenon of spiking may involve the penetration of the conductor metals such as Al into adjacent semiconductor structures, and this may result in short circuit defects damaging to device operation.
Additionally, according to conventional knowledge and practice, these barrier layers are of a nature effective to reduce top surface reflectivity for semiconductor devices, which is advantageous to permit effective operation of photolithographic techniques used in semiconductor manufacturing. In particular, the top surface of a barrier layer is of diminished reflectivity and can effectively reduce the comparatively high optically reflective surface of the electrical conductor material employed to make device interconnections within a particular integrated circuit device to an acceptable level. This diminished reflectivity improves the photolithographic patterning capability of the electrical conductor layer, as is conventionally recognized.
The barrier layers are additionally conventionally known to be effective for suppressing plastic flow of aluminum atoms during fabrication of integrated circuit devices, thereby becoming effective to prevent so-called "hillock" formations and to shunt current aside to minimize the risk of an open circuit developing from electromigration of conductor materials, or moreover even the stress-induced migration of conductor materials such as aluminum.
However, despite the above advantageous features and advantages of conventional barrier layers, their structures, and the methods for making them, there are problems encountered with the barrier layer structures and the methods for making them, according to the current and past state of the art of this technology. One such problem is that the barrier layers in past and current multi-layer IC structures require a disadvantageous thickness of the barrier metal layer itself to be effective in minimize "spiking". Traditional multi-layer IC structures rely upon particularly thick layers of TiW to reduce open circuit defects due to electro-migration from the electrical conductor used for electrical interconnections within IC structures. Current TiW thicknesses may be acceptable with semiconductor processes having junction depths greater than 0.2 micrometers, wherein spiking is not a primary concern. With such processes, current thicknesses of the barrier layers provides no significantly prohibitive problem.
Unfortunately, spiking becomes a more significant problem with structures defined by semiconductor processes directed toward junction depths of less than 0.2 micrometers. In particular, submicron processes are subject to more severe constraints.
Additionally, the barrier layer which is electrically conductive can react with the primary electrical conductor, reducing electrical conductivity of the entire conductor structure. This can be controlled by passivating the interface between the barrier metal and the primary electrical conductor.
An additional problem encountered with barrier layer fabrication relates to the temperature processing steps which must be used in later fabrication steps to preserve the structures already fabricated. As is well known, selecting a semiconductor process defines the basic parameters of the structures and materials which can be used, including their dimensions and their intermediate processing. Traditionally, nitrided TiW (TiW:N) can be formed by using rapid thermal annealing (RTA) in N.sub.2 or NH.sub.3 ambient or reactive sputtering techniques. Further, the ideal temperature range for reaction of non-porous saturated TiW:N layers using RTA is 700.degree.-900.degree. C.
However, this approach is limited to a first application of a layer of TiW:N. Once a subsequent conductor layer, e.g. Al, is deposited, the temperature range for subsequent manufacturing methods is very restricted, and a processing range of 700.degree.-900.degree. C. is no longer tenable. Thus, for any further layers of TiW:N which are thereafter desirable, fabrication must then be typically conducted according to a process such as reactive sputtering, which can employ lower temperature processing.
Unfortunately, reactive sputtering at these lower temperatures results in a TiW:N layer of high diffusivity which is especially susceptible to spiking. Compared to structures fabricated according to RTA processing, a much thicker layer of TiW:N is required to provide a wider barrier margin against defects, when lower temperature processes are employed. The enhanced thickness of the barrier layer of TiW:N which must be employed to address the increased likelihood of defects of course results in additional processing which is coupled with no significant advantages, a step which for example does not make the final structures fabricated have any added current carrying capacity.
Thus, an object of this invention is the development of improved diffusion barrier structures employing TiW and TiW:N alloy layers, which are functionally effective, economical to employ, and are not subject to current disadvantages and limitations.